Georgia Institute of Technology
CS4290/CS6290/ECE4100/ECE6100
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Do we have to model the wrong path or pipeline flush on branch misprediction ?
No. Given we have a simple trace driven simulator, we do not model wrong path. Also, as we stall fetch for branch misprection at the FETCH stage, we do not need to flush pipeline when a mispredicted branch gets executed (we simply need to resume fetch.
What is the TLB hit/miss penalty? Is the TLB blocking or non-blocking?
There is no penalty for TLB hit. For TLB miss, the penalty will be to load the PTE from memory. The TLB is blocking, therefore the pipeline will be stalled on a TLB miss, and release the stall until the TLB is filled with the correct translation.
The TLB in lab3 has been changed from non-blocking into blocking!
Therefore, on a TLB miss, the memory instruction will stay inside the memory stage(EX_latch) and the pipeline will be stalled.
The memory stage will check if the PTE is inside the dcache, if not, it will insert a memory request for PTE (a cache block size) into MSHR.
When the PTE request is returned, the TLB will be filled with the correct translation.
The returned memory block is also inserted inside the dcache just like other memory requests.
On the next cycle, the memory instruction will get a TLB hit and then it will access the dcache as usual.
Therefore, no replay is needed, and no piggyback on the PTE request is possible.
Do we need to install the PTE cache line into dcache?
Yes. Loading the PTE from memory is handled like a regular load instruction. Thus, it will be cached and if PTE is not in the cache, the MSHR will handle loading it from DRAM.
Do we need to reissue a memory instruction if there was a TLB miss?
No. The TLB is blocking, therefore the pipeline will be stalled and the instruction that generated the TLB miss will wait inside the memory stage until the TLB is filled with the correct translation.
How to count TLB hit/miss? Can an instruction increment the counters multiple times?
The counters are incremented only on the first try to access the TLB. Therefore, each instruction can only increment one of the counter by 1. This means that, for a TLB miss, after the TLB is filled with the correct translation, the second time memory stage access the TLB to get the translation will not furture increment the TLB hit counter.