Tutorial on Ocelot and SST-MacSim Simulator

Held in conjuction with ICPADS 2013 Conference

Dec. 15, 2013


The purpose of this tutorial is to provide an introduction to two recent GPGPU research infrastructures - Ocelot and SST-MacSim.

GPU Ocelot is an open-source dynamic JIT compilation framework for GPU compute applications targeting a range of GPU and non-GPU execution targets. Ocelot supports CUDA applications and provides an implementation of the CUDA Runtime API enabling seamless integration with existing CUDA applications. Its JIT compiler supports four backend execution targets - (1) an emulator that implements NVIDIAs Parallel Thread Execution (PTX) instruction set architecture, (2) NVIDIA, (3) AMD GPUs, and (4) a translator to LLVM for efficient execution of GPU kernels on multicore CPUs. An event trace analyzer is used with the emulator to generate instruction traces for driving microarchitecture timing simulators.

The Structural Simulation Toolkit (SST) is a component-based parallel architecture simulation infrastructure developed at Sandia National Laboratories in US. It is being used to enable the design space exploration of Exascale Computing architectures by integrating core, network and memory system models. As one of the architectural components in SST, MacSim is a trace-driven cycle-level simulator for heterogeneous architectures. SST-MacSim is configured to be driven by instruction traces of CUDA's PTX and Intel's x86 instructions. The CUDA traces are generated using the event trace analyzers integrated with the PTX emulator distributed with Ocelot. MacSim provides timing models for microarchitectural components of heterogeneous architectures so users can model alternative CPU+GPGPU architectures.

In this tutorial, in the morning session we provide overview of Ocelot, SST and MacSim. In the afternoon session, we will cover i) the detailed internal architecture of MacSim, ii) the use of the infrastructure to address an example research problem, and iii) a "how to" segment that covers common modifications to both Ocelot and MacSim for exploring research problems of common interest to the architecture and compiler community.


For more details on ICPADS here


Hyesoon Kim (Georgia Tech)


Hyesoon Kim, Jaewoong Sim, Joo Hwan Lee (Georgia Tech)


Tentative Schedule

Morning (9:00-12:30)

  • Part-I: 1.5hr: Overview of Ocelot Architecture

  • Part-II: 0.5 hr: Ocelot - Supported Devices

  • Part-III: 1.0hr: Overview of Macsim Lunch

    afternoon (2:00 - 5:00)
  • Part IV: 1.5hr: Details of MacSim simulator Break
  • Part V: 0.5hr: Case studies using SST-MacSim [slides]
  • Part VI: 1hr: Discussions of using MacSim and Ocelot