MSPC 2013
ACM SIGPLAN Workshop on Memory Systems Performance and Correctness
June, 2013 – Seattle, Washington – Co-located with PLDI 2013

Call for Papers (HTML, text)
Organizing Committee
Final Program
Final Paper Guidelines
Past Workshops

Paper Submission
March 15, 2013
March 31, 2013 (no more extension)
April 26, 2013
Final Submission
May 14, 2013

Organizing Committee

General Chair

Gabriel Loh, AMD

Program Chair

Hyesoon Kim, Georgia Tech
Daniel Chavarria, Pacific Northwest National Lab

Program Committee

John Cavazos, University of Delaware
Daniel Chavarria, Pacific Northwest National Lab
Philippe Clauss, INRIA
Boris Grot, EPFL
Jeff Hammond, Argonne National Lab
Hillery C Hunter, IBM
Costin Iancu, Lawrence Berkely National Laboratory
Hyesoon Kim, Georgia Tech
Minjang Kim, Qualcomm
Jim Larus, Microsoft Research
Jaejin Lee, Seoul National University
Wenjing Ma, Chinese Academy of Sciences
Mayur Naik, Georgia Tech
Satish Narayanasamy, University of Michigan
Lawrence Rauchwerger, Texas A&M
Vijay Reddi, UT-Austin
Xipeng Shen, William and Mary
Antonino Tumeo, Pacific Northwest National Lab
Jeffery Vetter, Oak Ridge National Lab & Georgia Tech
Uzi Vishkin, University Maryland

Steering Committee

Emery Berger, UMass Amherst
Brad Chen, Google
Trishul Chilimbi, Microsoft Research
Chen Ding, Rochester
Madan Musuvathi, Microsoft Research
Onur Mutlu, Carnegie Mellon University
Xipeng Shen, College of William & Mary
Jeffrey S. Vetter, Oak Ridge National Lab & Georgia Tech
Ben Zorn, Microsoft Research

Web and Submissions Chairs

Jaekyu Lee, Georgia Tech