MSPC 2013
ACM SIGPLAN Workshop on Memory Systems Performance and Correctness
June, 21, 2013 – Seattle, Washington – Co-located with PLDI 2013

Call for Papers (HTML, text)
Organizing Committee
Final Program
Final Paper Guidelines
Past Workshops

Paper Submission
March 15, 2013
March 31, 2013 (no more extension)
April 26, 2013
Final Submission
May 14, 2013

Final Program TBD

9:00-9:15 Opening Remarks: General Chair
9:15-9:30 Program Chairs' Note
9:30-10:30 Keynote: Xipeng Shen, William and Mary - Data Locality for Massive Parallelism
10:30-11:00 Break
11:00-12:15 Session 1: Consistency & Hardware Optimizations

Session Chair: TBD

Sequential Consistency for Heterogeneous-Race-Free: Programmer-Centric Memory Models for Heterogeneous Platforms
Derek Hower, Brad Beckmann, Ben Gaster, Blake Hechtman, Mark Hill, Steve Reinhardt and David Wood (AMD Research)

APE: Accelerator Processor Extensions to optimize data-compute co-location
Ganesh Venkatesh (Intel)

An Analytical Model to Predict Performance Impact of DRAM Bank Partitioning
Donguk Kim, Seokju Yoon and Jae W. Lee (Sungkyunkwan University, Korea)

12:15-1:30 Lunch
1:30-2:20 Session 2: Memory Allocation & Management I

Session Chair: TBD

A Study of Data Structures with a Deep Heap Shape
Haggai Eran, Erez Petrank (Technion - Israel Institute of Technology) (ACM DL Link) (slides) (poster) -->

Introducing Kernel-Level Page Reuse for High Performance Computing
Sébastien Valat, Marc Pérache (CEA), William Jalby (University de Versailles) (ACM DL Link) (slides) (poster) -->

2:20-3:10 Session 3: Memory Allocation & Management II

Session Chair: TBD

A Low Overhead Method for Recovering Unused Memory Inside Regions
Matthew Davis, Peter Schachte, Zoltan Somogyi, Harald Søndergaard (The University of Melbourne) (ACM DL Link) (slides) (poster) -->

Software-Controlled Transparent Management of Heterogeneous Memory Resources in Virtualized Systems
Min Lee, Vishal Gupta, Karsten Schwan (Georgia Institute of Technology) (ACM DL Link) (slides) (poster) -->

3:10-3:30 Break
3:30-4:40 Session 4: Poster Presentations

Session Chair: TBD

Program-Centric Cost Models for Locality
Guy Blelloch, Jeremy Fineman, Phillip Gibbons and Harsha Vardhan Simhadri (Carnegie Mellon University, MIT, Intel Labs Pittsburgh)

A new perspective on processing-in-memory architecture design
Dongping Zhang, Nuwan Jayasena, Joseph Greathouse, Mitesh Meswani, Mark Nutter, Alexander Lyashevsky and Mike Ignatowski (AMD)

A Coldness Metric for Cache Optimization
Raj Parihar, Chen Ding and Michael Huang (University of Rochester)

All-window Data Liveness
Pengcheng Li and Chen Ding (University of Rochester)

Software-level Scheduling to Exploit Non-uniformly Shared Data Cache on GPGPU
Bo Wu, Weilin Wang and Xipeng Shen (The College of William and Mary)

Cache Rationing for Multicore
Jacob Brock and Chen Ding (University of Rochester)

Analyzing Locality of Memory References in GPU Architectures
Saurabh Gupta, Ping Xiang, Huiyang Zhou (North Carolina State University)

4:40-5:30 Session 5: Poster & Discussion


Data Locality for Massive Parallelism
Xipeng Shen, William and Mary

Recent years have seen a rise of massive parallelism in modern processors, typified by Graphic Processing Units (GPU), Many Integrated Cores (MIC), Accelerated Processing Units (APU), and so on. As parallelism continues increasing fast, memory bandwidth expansion lags behind, causing an ever growing gap between memory bandwidth and the cumulated computing power in a machine. Consequently, effectively bringing data to cores is one of the most critical challenges for tapping into the potential of future systems. It is also a key to power efficiency as data movements are expected to consume more than half of power in future computing systems. This talk discusses the important role of data locality enhancement in meeting the challenges. It examines the implications massive parallelism brings to data locality, and some recent progress in the measurement, modeling, and exploitation of data locality. It concludes with a list of open questions and research directions.

Xipeng Shen is the Adina Allen Term Distinguished Associate Professor in the College of William and Mary, an IBM Center for Advanced Studies (CAS) Faculty Fellow, a Visiting Researcher at Intel Labs. His research in data locality and massive parallelism received the prestigious Early Career Research Award from the US Department of Energy in 2011 and the Best Paper Award at ACM PPoPP 2010. His research in input-centric program dynamic optimizations received the CAREER Award from the US National Science Foundation in 2010. Xipeng Shen's research lies in the broad field of programming systems, with an emphasis on enabling extreme-scale data-intensive computing and intelligent portable computing through innovations in both compilers and runtime systems. He has been particularly interested in capturing large-scale program behavior patterns, in both data accesses and code executions, and exploiting them for scalable and efficient computing in a heterogeneous, massively parallel environment.