Transparent Hardware Management of Stacked DRAM as Part of Memory
Jaewoong Sim, Alaa R. Alameldeen, Zeshan Chishti, Chris Wilkerson, Hyesoon Kim
Proceedings of the 47th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), Cambridge, UK, Dec. 2014[talks]

GPUMech: GPU Performance Modeling Technique based on Interval Analysis
Jen-Cheng Huang, Joo Hwan Lee, Hyesoon Kim, Hsien-Hsin S. Lee
Proceedings of the 47th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), Cambridge, UK, Dec. 2014 [talks]

Design space exploration of memory model for heterogeneous computing
Jieun Lim and Hyesoon Kim
2014 IEEE 26th International Symposium on Computer Architecture and High Performance Computing(SBAC-PAD), Oct. 2014[talks]

OpenCL Performance Evaluation on Modern Multi Core CPUs
Joo Hwan Lee, Kaushik Patel, Nimit Nigania, Hyojong Kim, Hyesoon Kim,
Scientific Programming, 2014

Power Modeling for GPU Architectures Using McPAT
Jieun Lim, Nagesh B. Lakshminarayana, Hyesoon Kim, William Song, Sudhakar Yalamanchili, and Wonyong Sung
ACM Trans. Des. Autom. Electron. Syst. 19, 3, Article 26 (June 2014)

Harmonica: An FPGA-Based Data Parallel Soft Core
Chad Kersey, Sudhakar Yalamanchili, Hyojong Kim, Nimit Nigania, and Hyesoon Kim
The 22nd International Symposium on Field-Programmable Custom Computing Machines (FCCM), May, 2014 (Poster)

A Configurable and Strong RAS Solution for Die-Stacked DRAM Caches
Jaewoong Sim, Gabriel H. Loh, Vilas Sridharan, Mike O'Connor
IEEE Micro, Special Issues: Micro's Top Picks from 2013 Computer Architecture Conferences (TOP PICKS), May/June 2014

Hardware Support for Safe Execution of Native Client Applications
Dilan Manatunga, Joo Hwan Lee, and Hyesoon Kim
Computer Architecture Letters (CAL), vol.PP, no.99, pp.1,1 2014

Spare Register Aware Prefetching for Graph Algorithms on GPUs
Nagesh B Lakshminarayana and Hyesoon Kim
The 20th International Symposium on High Performance Computer Architecture (HPCA), Orlando, Feb 2014 [talks]

TBPoint: Reducing Simulation Time for Large Scale GPGPU Kernels
Jen-Cheng Huang, Lifeng Nai, Hyesoon Kim, Hsien-Hsin Lee
The 28th International Parallel & Distributed PRocessing Symposium (IPDPS), Phoenix, AZ, May 2014 Design Space Exploration of On-chip Ring Interconnection for a CPU-GPU Heterogeneous Architecture
Jaekyu Lee, Si Li, Hyesoon Kim, and Sudhakar Yalamanchili
In Journal of Parallel and Distributed Computing (JPDC), Vol. 73, Issue 12, pp. 1525-1538, December 2013

Adaptive Virtual Channel Partitioning for Network-on-Chip in Heterogeneous Architectures
Jaekyu Lee, Si Li, Hyesoon Kim, and Sudhakar Yalamanchili
In ACM Transactions on Design Automation of Electronic Systems (TODAES), Vol. 18, No. 4, pp.48:1-48:28, October 2013

SESH framework: A Space Exploration Framework for GPU Application and Hardware Codesign
Joo Hwan Lee, Jiayuan Meng, Hyesoon Kim
4th International Workshop on Performance Modeling, Benchmarking and Simulation of High Performance Computer Systems (PMBS), held as part of SC13, Denver, Colorado, USA, November 2013

Resilient Die-stacked DRAM Caches
Jaewoong Sim, Gabriel H. Loh, Vilas Sridharan, Mike O'Connor
40th international Symposium on Computer Architecture (ISCA), Tel-Aviv, Israel, June 2013 [talk]

CHiP: A Profiler to Measure the effect of Cache Contention on Scalability
Bevin Brett, Pranith Kumar, Minjang Kim, Hyesoon Kim,
Workshop on Multithreaded Architectures and Applications in conjunction with IPDPS-27, Boston, USA, May 2013

OpenCL Performance Evaluation on Modern Multi Core CPUs
Joo Hwan Lee, Kaushik Patel, Nimit Nigania, Hyojong Kim, Hyesoon Kim,
Multicore and GPU Programming Models, Languages and Compilers Workshop (PLC 2013), in conjunction with IPDPS-27, Boston, USA, May 2013

When Prefetching Works, When It Doesn't, and Why
Jaekyu Lee, Hyesoon Kim, and Richard Vuduc
An invited paper (originally published in TACO), 8th International Conference on High-Performance and Embedded Architectures and Compilers (HiPEAC), Berlin, Germany, January 2013 A Mostly-Clean DRAM Cache for Effective Hit Speculation and Self-Balancing Dispatch
Jaewoong Sim, Gabriel Loh, Hyesoon Kim, Mike O'Connor, Mithuna Thottethodi
Proceedings of the 45th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), Vancouver, BC, Canada, Dec. 2012 [talk]

SD3: An Efficient Dynamic Data-Dependence Profiling Mechanism
Minjang Kim, Nagesh B. Lakshminarayana, Hyesoon Kim, Chi-Keung Luk
IEEE Transactions on Computers (TC), July 2012.

FLEXclusion: Balancing Cache Capacity and On-chip Bandwidth with Flexible Exclusion
Jaewoong Sim, Jaekyu Lee, Moinuddin K. Qureshi, and Hyesoon Kim
Proceedings of the 39th IEEE International Symposium on Computer Architecture (ISCA), Portland, OR, June 2012 [talk]

Predicting Potential Speedup of Serial Code via Lightweight Profiling and Emulations with Memory Performance Model
Minjang Kim, Pranith Kumar, Hyesoon Kim, and Bevin Brett
Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium (IPDPS), Shanghai, China, May 2012

When Prefetching Works, When It Doesn't, and Why
Jaekyu Lee, Hyesoon Kim, and Richard Vuduc
ACM Transactions on Architecture and Code Optimization (TACO), Vol. 9, No. 1, pp.2:1-2:29, March 2012

A Performance Analysis Framework for Identifying Potential Benefits in GPGPU Applications
Jaewoong Sim, Aniruddha Dasgupta, Hyesoon Kim, and Richard Vuduc
Proceedings of the 17th ACM SIGPLAN Symposium on Principles and Practice of Parallal Programming (PPoPP), New Orleans, LA, February 2012. [talk]

TAP: A TLP-Aware Cache Management Schemes for a CPU-GPU Heterogeneous Architecture
Jaekyu Lee and Hyesoon Kim
Proceedings of the 18th International Symposium on High Performance Computer Architecture (HPCA), New Orleans, LA, February 2012. [talk] DRAM Scheduling Policy for a GPGPU Architecture Based on a Potential Function
Nagesh B. Lakshminarayana, Jaekyu Lee, Hyesoon Kim, and Jinwoo Shin
IEEE Computer Architecture Letters (CAL) Nov. 2011 Many-Thread Aware Prefetching Mechanisms for GPGPU Applications
Jaekyu Lee, Nagesh B Lakshminarayana, Hyesoon Kim, Richard Vuduc
MICRO-43, Atlanta, GA, 2010. [talk]

SD3: A scalable Approach to Data-Dependence Profiling
Minjang Kim, Hyesoon Kim, Chi-Keung Luk
MICRO-43, Atlanta, GA, 2010.

An Integrated GPU Power and Performance Model
Sunpyo Hong and Hyesoon Kim
ISCA-37, June 2010. [talk]

Prospector: A Dynamic Data-Dependence Profiler To Help Parallel Programming
Minjang Kim, Hyesoon Kim, Chi-Keung Luk
HotPar-2, June, 2010. [poster]

Effect of Instruction Fetch and Memory Scheduling on GPU Performance
Nagesh B. Lakshminarayana and Hyesoon Kim
Workshop on Language, Compiler, and Architecture Support for GPGPU, in conjunction with HPCA/PPoPP 2010, 2010. [talk] Qilin: Exploiting Parallelism on Heterogeneous Multiprocessors with Adaptive Mapping
Chi-Keung Luk, Sunpyo Hong, Hyesoon Kim
MICRO 2009, December, 2009.

Age Based Scheduling Policy for Asymmetric Multiprocessors
Nagesh B. Lakshminarayana, Jaekyu Lee, Hyesoon Kim
Super Computing ,November, 2009. [talk]

An Analytical Model for a GPU Architecture with Memory-level and Thread-level Parallelism Awareness
Sunpyo Hong and Hyesoon Kim
Proceedings of the 36th International Symposium on Computer Architecture (ISCA-36), Austin, TX, June 2009. [talk]

Understanding Performance, Power and Energy Behavior in Asymmetric Multiprocessors
Nagesh B. Lakshminarayana and Hyesoon Kim
2008 IEEE International Conference on Computer Design (ICCD), Oct 2008. [talk]

Asymmetry Aware Scheduling Algorithms for Asymmetric Multiprocessor
Nagesh Lakshminarayana, Sushma Rao, Hyesoon Kim
Workshop on the Interaction between Operating Systems and Computer Architecture (WIOSCA), Beijing, China, June 2008. [talk]
  • Joo Hwan Lee, Nimit Nigania, Hyesoon Kim, and Bevin Brett, "HPerf : A Lightweight Profiler for Task Distribution on CPU+GPU Platforms", GT-CS-15-04, Georgia Institute of Technology, 2015.

  • Jaekyu Lee, Si Li, Hyesoon Kim, and Sudhakar Yalamanchili, "Design Space Exploration of On-chip Ring Interconnection for a CPU-GPU Architecture", GIT-CERCS-12-05, Georgia Institute of Technology, 2012.

  • Chayong Lee, Euna Kim, and Hyesoon Kim, "The AM-Bench: An Android Multimedia Benchmark Suite", GIT-CERCS-12-04, Georgia Institute of Technology, 2012.

  • Vishal Gupta, Hyesoon Kim, and Karsten Schwan, "Evaluating Scalability of Multi-threaded Applications on a Many-core Platform", GIT-CERCS-12-03, Georgia Institute of Technology, 2012.

  • Minjang Kim, Chi-Keung Luk, Hyesoon Kim, "Prospector:Discovering Parallelism via Dynamic Data-Dependence Profiling", TR-2009-003, Georgia Institute of Technology, 2009.

  • Sunpyo Hong, Hyesoon Kim, "An Analytical Model for a GPU Architecture with Memory-level and Thread-level Parallelism Awareness", TR-2009-003, Georgia Institute of Technology, 2009.

  • Sunpyo Hong, Hyesoon Kim, "Parallelization of Mutual-Information Based Registration in the ITK Toolkit Using CUDA and TBB", TR-2009-002, Georgia Institute of Technology, 2009.

  • Chi-Keung Luk, Sunpyo Hong, Hyesoon Kim, "Qilin: Exploiting Parallelism on Heterogeneous Multiprocessors with Adaptive Mapping", TR-2009-001, Georgia Institute of Technology, January, 2009.